The complexity of integrated circuits have dramatically increased over the years. Smaller and smaller devices are required for the integrated circuit technology. A major problem in these very dense integrated circuits is the electrical contacts to the various elements and devices in the integrated circuit. The electrical contacted elements and devices of the integrated circuit must then be electrically connected through various levels of metallurgy to other devices within the integrated circuit.
It is known to use highly doped polycrystalline silicon as the source of a dopant for regions of monocrystalline silicon to form PN junctions therein. The polycrystalline silicon can either be removed or allowed to become part of the device as the electrical contact for the region formed by the out-diffusion from that polycrystalline silicon. The processes are taught, for example, by D. M. Duncan U.S. Pat. No. 3,978,515; J. H. Scott, Jr. U.S. Pat. No. 3,460,007; D. M. Duncan U.S. Pat. No. 3,664,896; S. Tauchi et al. U.S. Pat. No. 3,484,313 and I. T. Ho et al. U.S. Pat. No. 4,209,350. However, these patents are either silent on the method for the next level metallurgy to that electrical contact or have a second level metallurgy directly above the polycrystalline silicon electrical contact to the PN junction.
Other workers in the field have addressed the electrical contact, such as the U.S. Pat. No. 3,600,651, by providing lateral polycrystalline silicon contacts to a monocrystalline silicon active region. The polycrystalline silicon is then contacted at a more convenient location laterally away from the active region. N. G. Anantha et al. U.S. Pat. No. 4,236,294 also uses the technique of a polycrystalline silicon contact to a PN region and then a contact to the polycrystalline silicon layer at some convenient distance laterally away from that PN region.